• Technology
Technology Roadmap
Backgrind(Wafer Thinning) Available 2018 1H 2018 2H 2019
Non-Bumped Wafer (STD Process) 60um 55um 55um 50um
Non-Bumped Wafer (GAL Process) 30um 25um 25um 20um
Bumped Wafer 200um 150um 150um 130um
Non-Bumped Wafer 6um 5um 5um 3um
Bumped Wafer 20um 15um 15um 10um
Wafer Dicing Available 2018 1H 2018 2H 2019
Blade Dicing 50um 45um 45um 40um
Laser Groove 60um 55um 55um 50um
Laser Groove (W/O B/G_780umT) 65um 60um 60um 55um
Stealth Dicing 10um 10um 10um 10um
Die Attach Available 2018 1H 2018 2H 2019
Die To Substrate 10um 5um 5um 5um
Die To Die 10um 5um 5um 3um
Film On Wire 50um 45um 45um 40um
Film On Die 110um 100um 90um 80um
Epoxy 0.5mm 0.4mm 0.3mm 0.25mm
DAF 1.5mm 1.0mm 0.8mm 0.7mm
Epoxy 75um 70um 65um 60um
DAF 30nm 25nm 20nm 15nm
Wire Bonding Available 2018 1H 2018 2H 2019
Au Wire 28nm 28nm 28nm 22nm
Cu Wire 45nm 32nm 28nm 28nm
Au Wire 7000Å 7000Å 6500Å 6000Å
Cu Wire 8000Å 8000Å 7500Å 7000Å
Au Wire Ag88% & Ag95% Ag 95% Ag 96% Ag 99%
Cu Wire Pd-coated 0.7mils Pd-coated 0.6mils
Min. Bond Pad Open / Pitch (0.7mil) 40um / 45um 40um / 45um 35um / 40um 35um / 40um
Forward 45um 45um 40um 35um
Reverse 30um 30um 25um 25um
2200um 2400um 2600um 2700um
800um 1200um 1500um 2000um
Mold Available 2018 1H 2018 2H 2019
Thickness 0.25mmT 0.23mmT 0.20mmT 0.20mmT
Clearance 70umT 70umT 50umT 50umT
Thickness 0.25mmT 0.21mmT 0.20mmT 0.20mmT
Clearance 140umT 130mmT 120mmT 120mmT
SMT Available 2018 1H 2018 2H 2019
Size 01005
Height 200um 200um 150um 100um
Pitch (Clearance) 150um 150um 130um 100um
Double Side Cap. Mount Top Side Cap. Mount Land Side Cap. Mount Land Side Cap. Mount Both Side Cap. Mount
Bump Available 2018 1H 2018 2H 2019
CD size 22um(20um) 22um(20um) 20um(12um) 15um(10um)
Thickness 3um~5um 3um ~10um
Line / Space 15um/15um 9um/9um 8um/8um
Thickness 9um 20um 30um
Thickness 10um(10um) 20um(10um) 30um (10um)
Cure temp. STD. 365℃ Low cure 230℃ Low cure 200℃
UBM Thickness 3um, 5um, 8um 10um, 15um, 20um
Ball pitch 350um 300um 250um
*SnAg pitch 150um 100um
Pitch 50um 40um 30um
CD size 20um 15um 10um
  • Backside image after backgrinding

  • After tape mounting on ringframe

  • Wafer warpage after backgrinding to 50um thickness

  • Using a grinding wheel, backgrinding is one of packaging steps to make wafer thinner for stacking.
    Currently, wafers are thinned 75μm thickness below for multi-stacking. Hana Micron has two kinds of machines: wet and dry polishing.
    Prior to grinding, wafers are laminated with UV backgrinding tape to prevent surface damage on the top of a wafer.
    This backgrinding process is also known as backlap.
Wafer Sawing
  • [ Wafer sawing ]

  • [ Laser coating ]

  • Wafer sawing is a process which separates a wafer into chips.
    There are two sorts of the sawing processes:
    mechanical sawing or laser cutting.
    Before dicing, a wafer is attached on dicing tape with UV or PS property.
    In the case of mechanical sawing, a diamond blade which is rotating at high speeds to cut the wafer along the scribe lane is used.
    With low-K wafers, Hana Micron has used a laser groove to separate the chips.
Chip stacking
  • Die attach machine

  • 16 chip stack using
    25um thickness chips

  • Die attach is the process of attaching the silicon chip on the PCB or lead-frame of the semiconductor package after wafer sawing.
    Adhesive consists of a mixture of silica powder and epoxy.
    Die attach-cure is completed in the oven at high temperatures within proper cure times.
    Also die attach film such as DDF and WBL can be used for die to die stack.
    The advanced technology of die attach is to pickup the thin die below 50um thickness.
    Hana Micron uses a special one called “thin die kit” to make it easier to pick up.
  • Thin die pickup process

SMT process
  • SMT (Surface Mount Technology) is the process for making electronic circuits in which the components are
    mounted directly on the surface of PCB.
    The trends of SMT are smaller component size and fine pitch design rule.
    Chips containing integrated circuits may be stacked vertically on a substrate.
    They are internally connected by
    fine wires that are bonded to the package.
    Alternatively, solder bumps are used to join stacked chips together with
    flip chip technology.
    The SIP package performs all or most of the functions of an electronic system, and are
    typically used inside a mobile phone, digital music player, and so on.
Flipchip Process
  • Flipchip FBGA (FcFBGA)

  • Flipchip is a method that interconnects with the chips and PCB without a wire bonding process.
    By using the entire
    die surface to establish interconnect, the need for wire bond interconnect is eliminated and the package size can be
    More importantly, high performance applications are directly connected the die to a substrate or a board:
    the short signal path is to reduce the interconnect, inductance, and capacitance, all of which greatly improves the
    electrical performance.
    The flipchip has solder bumps that are deposited on the chip pads on the top of the wafer
    during the final processing step.
    The chip with bumps is flipped and bonded on the PCB.
    It allows to heat transfer
    into a chamber for soldering.
    Generally, flipchip is developed Cu pillar below 80um fine pitch.
  • Flipchip BGA (FcBGA) with heat spreader

Wire Bonding
  • The wire bonding process is a method to make interconnections between the chip pad and the PCB using wires that are composed of Au, Al, and Cu.
    Wire bonding is considered the most cost-effective and flexible interconnect technology, and is used to assemble the huge majority of semiconductor packages.
    According to market requirements, the bond-pads pitch between the device chips was continuously reducing while device technology moved towards nano-IC technologies.
    Hana Micron has made mass production of 45um pitch bond pad. 40um pitch one is also developed.
  • [ In line : 45um pitch ]

  • [ In-line Fine Pitch ]

  • [ Multi-tiers Fine Pitch ]

  • Also, copper wire has become the more important material for various packaging in the assembly industry because it has superior signal integrity and cost savings compared to gold.
  • In terms of productivity and anti-oxidation, palladium–coated copper wire is so excellent that it is used in high performance
    package at Hana Micron
  • Molding is the process of encapsulating the device using plastic materials consisting of EMC(Epoxy Molding Compound).
    This helps protect the device from mechanical and chemical damage after the wire bonding process.
    There are three kinds of molding processes: transfer molding, top gate molding, and compression molding.
  • Transfer Molding

    This is the most common molding process but it cannot be used at special package.

    • Top Gate Molding

      This process can only be used for POP package.
      The molding process encapsulates the strip area partially

      • Compression Molding

        This process uses EMC which is the powder type.
        It’s possible to mold a device through thin mold
        clearance as well as prevent wire sweeping.
        But the
        machine cost is very expensive

        • Molding (cont.)

          For flipchip molding, filling the narrow bump gaps was developed to MUF(Molded UnderFill) in which the process are reduction and simplification in cost and filling process, respectively.
          The MUF process can be applied to flipchip below 50um bump height of cu pillar.

          Solder Ball Attach
          • After flux printing, 0.2mm to 0.5mm solder ball, which is made of Sn-Ag-Cu, is mounted on the PCB ball land.
            Solder balls are easily mounted on the pattern of PCB ball land by doing a reflow along IR rail.
            After the ball mount and IR-reflow, the device is cleaned by using a solvent or water.
            Hana Micron has developed FBGA package which is 0.4mm and 0.2mm in pitch and diameter, respectively.
          • [ FBGA with solder ball ]

          • [ Solder ball attach process ]

            POP Process
            • Stacking package is a process to interconnect different kinds of packages.
              POP (Package-on-Package) is typically a
              combination of memory and ASIC, baseband, and AP packages; each package should combine together vertically
              with reflow, then each package is mounted on the board.
            • [ POP schematic ]

            • [ POP package ]

            • [ POP Interconnection ]

            • LDP(Laser Drill Process) can be used for the bottom one of POP.
              It is a process to make I/O paths on the bottom surface
              of POP.
              After the molding process, the laser drills holes on the package surface to expose land pads.
              With LDP, it should
              get high I/O density and low warpage.
              Hana Micron has the advanced technology to make the ball pitch of 0.4mm for
              POP bottom packaging.
            • [ POP bottom package ]

            • [ After laser drilling ]

            • [ Ball shape after laser drilling ]

            WLP Process
            • Instead of the traditional process of assembling the package of each unit after wafer dicing, WLCSP refers to the technology of packaging an integrated circuit at wafer level.
              WLCSP has the following advantages: smaller size, less weight, relatively easier assembly process, lower production cost, and improvement in electrical performance.

              • [ Top Image ]

              • [ Bottom Image ]

              [ Backside lamination process ]